Regviz

Espressif Systems /ESP32 /SPI0 /CTRL1

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CTRL1

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Espressif Systems/ESP32/SPI0/CTRL1#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CS_HOLD_DELAY_RES0CS_HOLD_DELAY

Fields

CS_HOLD_DELAY_RES

Delay cycles of resume Flash when resume Flash is enable by spi clock.
CS_HOLD_DELAY

SPI cs signal is delayed by spi clock cycles

Links

()

Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data